Memory circuit with improved word line noise preventing circuits

ABSTRACT

A memory circuit provided with an improved word line noise preventing circuit is disclosed. 
     The memory circuit is one of the type having a pair of digit lines, a plurality of word lines intersecting with the digit lines, a plurality of memory cells, a sense amplifier coupled to the pair of digit lines and a plurality of noise preventing circuits provided for the word lines. The memory is featured in that the noise preventing circuits are disenabled during the period when the sense amplifier amplifies the voltage difference between the pair of digit lines.

BACKGROUND OF THE INVENTION

The present invention relates to a dynamic memory circuit employingfield effect transistors, and more particularly to a word line noisepreventing circuit for preventing a word line from being affected bynoise or the like.

Dynamic memories have been widely utilized in various fields because oflarge memory capacity and relatively low power consumption. In dynamicmemories, word lines are driven in a dynamic manner. Namely, all wordlines are reset to the ground potential in reset (or precharge) periodsand, in active periods, a selected one word line is driven to a powervoltage (Vcc) through a source-follower transistor while the remainingnon-selected word lines are left in a floating state. In other words,the non-selected lines are not connected to any voltage source in activeperiods. Therefore, the non-selected word lines are easily affected bynoise such as voltage change in digit lines. Particularly, rise ofpotential of digit lines having higher level (logic 1 level) to thepower voltage Vcc by active pull up circuits raise the potential of thenon-selected word lines. In this case, many memory cells which shouldnot be selected are erroneously accessed so that a plurality of storeddata are simultaneously read out to the each digit line, resulting indestruction of memory data stored in the memory cells.

In order to avoid the above problem due to the fluctuation in thepotentials of the non-selected word lines, word line noise preventingcircuits are provided to the respective word lines. The word line noisepreventing circuit maintains the potential of the non-selected word lineat the ground potential during active periods.

On the other hand, half the digit lines which have been charged to aprecharge voltage, such as the power voltage during a reset period, aredischarged to the ground potential by amplifying operation of senseamplifiers.

The discharge of the digit lines affects a potential of a substrate onwhich a memory is fabricated and potentials of memory cell capacitorsthrough coupling therebetween so that the potentials of the substrateand the memory cell capacitors are lowered.

Especially, in the memory cell storing logic "0" level, i.e. the groundpotential, the potential of the memory cell capacitors is lowered fromthe ground potential to a negative potential, and in the case where suchnegative potential is lower than the ground potential which is appliedto the non-selected word lines by a threshold voltage of memory celltransistors, the memory cell transistors having gates coupled to thenon-selected word lines become conducting. Thus, in addition to thememory cell transistors coupled to the selected word line, the memorycell transistors coupled to the non-selected word lines are erroneouslyrendered conductive, which means in other words a plurality of data froma plurality of memory cells are read out on the same digit line at thesame time. Accordingly, data stored in these memory cells are destroyeddue to mutual interference.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a memory circuitwhich can operate stably without causing data destruction ormalfunction.

The memory circuit according to the present invention is of the typehaving a plurality pairs of digit lines, a plurality of word linesintersecting with digit lines, a plurality of memory cells each coupledto one of the word lines and digit lines, a precharge circuit forprecharging the digit lines to a predetermined potential in resetperiod, a word selection circuit for selectively applying a drive signalonly to a selected word line, a plurality of sense amplifiers eachcoupled to each pair of digit lines for discharging the lower potentialside digit line of the digit line pair without materially dischargingthe higher potential side digit line of the same digit line pair and aplurality of word line noise prevention circuits each coupled to eachone of the word lines for clamping the non-selected word lines to areference potential such as the ground potential, and is featured inthat the word line noise prevention circuits are disenabled during afirst period when the sense amplifiers discharge the lower potentialside digit lines.

According to this feature, the word line noise prevention circuits aredisabled during the amplifying period by the sense amplifiers so thatthe clamping of the non-selected word lines is released. Accordingly,the non-selected word lines are allowed to be affected by the dischargeof the digit lines so that the potential of the non-selected word linesare lowered below the reference voltage as well as the fall of thepotentials of the memory cell capacitors. Therefore, the gate-sourcepotential of the memory cell transistors connected to the non-selectedword lines is not increased, thereby preventing the memory celltransistors coupled to the non-selected word lines from assuming aconductive state during the period when the sense amplifiers dischargethe digit lines. Thus, data destruction can be effectively avoided.

According to one aspect of the invention, the memory circuit is furtherprovided with a plurality of active pull-up circuits each coupled toeach pair of digit lines for operatively raising the higher potentialside digit line to the power voltage after the amplification by thesense amplifier, and the word line noise preventing circuit is enabledat least during the period when the active pull-up circuit operates.

The word line noise preventing circuit according to the presentinvention is composed of a first field effect transistor having acurrent path connected between a first node and a reference potentialsource, a series circuit of second and third field effect transistorsconnected in series between one of the word lines and the referencepotential source, the first and second transistors forming a flip-flopcircuit, and a precharge transistor for operatively precharging thefirst node, the third transistor controlling the noise preventingcircuit between the enabled state and the disabled state.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic circuit diagram showing a major part of a memorycircuit according to the prior art;

FIG. 2 is a timing chart showing operation of the memory circuit of FIG.1;

FIG. 3 is a schematic circuit diagram showing a major part of a memorycircuit according to one embodiment of the present invention;

FIG. 4 is a timing chart showing operation of the circuit in FIG. 3; and

FIG. 5 is a schematic diagram showing another embodiment of theinvention:

DETAILED DESCRIPTION OF THE INVENTION

With reference to FIGS. 1 and 2, a memory circuit according to the priorart is explained.

FIG. 1 shows a major part of a conventional dynamic memory circuit.

A pair of digit lines DL and DL are arranged in parallel, while a pairof dummy word lines DW₁ and DW₂ and a plurality of word lines WL₁ toWL_(n) are intersecting with the digit lines DL and DL. Dummy cells DMconsisting of FETs Q_(D1) and Q_(D2) and a capacitor C_(D) are connectedto the dummy word lines DW₁, DW₂ and the digit lines DL, DL while memorycells MC, each composed of a cell FET Q_(M) and a memory cell capacitorC_(S), are connected to the word lines WL₁ to WL_(n) and the digit linesDL and DL, in a known way. In FIG. 1, among many pairs of digit lines,one pair of digit lines DL and DL are representatively illustrated.

FETs Q₁ and Q₂ form a flip-flop type sense amplifier. FETs Q₃ to Q₈ andcapacitors C₁ and C₂ form an active pull-up circuit which raises apotential of the higher side digit line to a power voltage Vcc after theoperation of the sense amplifier.

FETs Q₉ to Q_(1l) form a precharge circuit for equally precharging thedigit lines DL and DL to Vcc.

FETs Q₁₂ and Q₁₃ are coupled between the digit lines DL, DL and a pairof bus lines I/O, I/ , respectively to make permit data-transfertherebetween when FETs Q₁₂ and Q₁₃ are rendered conductive by a columnselection signal Yi.

The word lines WL₁ to WL_(n) are selected row decoders RD₁ to RD_(n),respectively. The row decoder RD₁ is composed of a source-follower FETQ₁₇ connected in series between a timing signal source RA and the wordline WL₁, a NOR circuit having FETs Q_(D1) to Q_(DN) receiving rowaddress signals AX₀ (AX₀) to AX_(n) (AX_(n)) and a precharge FET Q₁₄,and a transfer FET Q₁₆ for connecting an output of the NOR circuit to agate of FET Q₁₅.

Other word decoders WD₂ to WD_(n) have the same structure, except forthe combination of address signals AX₀, AX₀ to AX_(n), AX_(n) appliedthereto. Word line noise preventing circuits NP₁ to NP_(n) are connectedto the word lines WL₁ to WL_(n), respectively.

The word line noise preventing circuit NP₁ is composed of a pair of FETsQ₁₇ and Q₁₈ forming a flip-flop circuit, a drain (N2) of FET Q₁₈ beingconnected to the word line WL₁, and a precharge FET Q₁₉ for precharginga node N₁ to Vcc. A substrate bias circuit 10 is formed on the samesemiconductor chip on which the memory circuit is fabricated. Thecircuit 10 receives an oscillation signal φ_(osc) to generate asubstrate bias (V_(SUB)) through a capacitor C_(B) and a diode D_(B) tobe applied to the substrate SUB in a known way.

FIG. 2 shows operation of the circuit of FIG. 1. At a time point t₁, theprevious access cycle is terminated and a reset period is initiated.

A reset precharge signal P is first raised to Vcc to render conductiveFETs Q₁₄ in each row decoder, Q₁₉ in each noise preventing circuit andQ_(D2) in each dummy memory cell. Thus, the dummy cells DM and the rowdecoders are reset for subsequent operations. Also in each noisepreventing circuits, the node N₁ is charged to Vcc to render FET Q₁₈conductive so that the word line connected to that noise preventingcircuit is clamped to the ground potential.

Subsequently, timing signals PDL₀ and PDL₁ are sequentially raised toVcc so that the digit lines DL and DL are equally precharged to Vcc andthe capacitors C₁ and C₂ are also precharged to Vcc through FETs Q₅ andQ₆.

At a time t₂, the timing signals P, PDL₀ and PDL₁ have fallen to theground potential to terminate the reset period and introduce an activeperiod.

Subsequently, in the active period, after the respective address signalsAX₀ (AX₀) to AX_(n) (AX_(n)) have established their logical states, acontrol signal XDT is raised to Vcc so that the gate potential of FETQ₁₅ is determined by the output of the NOR circuit in each row decoder.Then, after the gate potential of FET Q₁₅ has been determined, thesignal XDT is reduced to an intermediate voltage which is lower than Vccbut higher than a threshold voltage of FET Q₁₆.

Then the timing signal RA having Vcc is applied to the drain of FET Q₁₅in each row decoder at a time t₃. In this instance, the signal RA istransmitted through the row decoder in which the gate potential of FETQ₁₅ is high in level to a selected word line (e.g. WL₁) to set itapproximately at Vcc.

In this instance, in the word line noise preventing circuit e.g. NP₁,since the current capability of FET Q₁₉ is set smaller than that of FETQ₁₅, the potential at the node N2 is raised to discharge the node N1.Thus, FET Q₁₈ becomes non-conducting so that the selected word line e.g.WL₁ is raised to Vcc. While in the remaining noise preventing circuits(e.g. NP₂ to NP_(n)), the charge at the node N₁ is maintained withoutbeing discharged to keep FET Q₁₈ conductive. Thus, the non-selected wordlines (e.g. WL₂ to WL_(n)) are clamped to the ground potential so thatfluctuation in potential of the non-selected word lines can beeffectively avoided. In response to this selection of word line WL₁,data stored the capacitor C_(S) in the memory cell MC coupled to theselected word line is transferred onto the digit line e.g. DL. Also, thedummy word line e.g. DW₁ is simultaneously driven to Vcc by the decoderDWD₁ to connect the capacitor C_(D) to the digit line DL so that aslight change in potential is applied to DL. The change caused by thedummy cell is of an intermediate degree between the cases caused by thememory cells storing "1" and "0".

Subsequently, at a time t₄, a sense enable signal SE₁ has fallen fromVcc to the ground potential. In response to this, the sense amplifier(Q₁, Q₂) starts to discharge the lower potential side digit line (e.g.DL) without materially discharging the high potential side digit line(e.g. DL), thus discriminating the pair of digit lines into binary logiclevels. In this instance, the discharge of the lower potential sidedigit lines makes the substrate bias voltage V_(SUB) and the potentialV_(A) at the output node A of the memory cell capacitor C_(S) in each ofmemory cells lower through coupling between the digit lines and thesubstrate and the cell capacitors C_(S), as illustrated. Especially forthose memory cells storing "0" level, the potential V_(A) has fallen toa negative potential.

The the non-selected word lines are kept at the ground potential asexplained above. Accordingly, in the case where the fall of thepotential V_(A) at the node A is larger than a threshold voltage of thememory cell transistor Q_(M) in the memory cells storing "0" level, thememory cell transistor Q_(M) is forward-biased to take a conductivestate even though the word line connected thereto is of the non-selected(ground) level. Accordingly, a plurality of data stored in a pluralityof memory cells are read out on to the same digit line in this case sothat data of the memory cells are destroyed due to mutual interferenceamong a plurality of memory cells.

The above fall in potentials of the substrate and the memory cellcapacitors gradually recovers to return to their initial potentials dueto a supply of charge to the substrate from the substrate bias circuit10.

Subsequently, at a time t₅, the active pull-up circuits start theiroperations in response to a rise of a timing signal SE 2. Particularly,in the case where DL and DL are at "0" and "1" level, respectively, FETQ₄ is conducting and hence the potential at a node N₃ is discharged tothe ground potential so that FET Q₃ becomes non-conductive state, whileFET Q₇ is not conductive so that the rise of SE 2 is superposed on thepreviously charged level (Vcc) at a node N₂ so that the potential at thenode N₄ rises above Vcc thereby to render FET Q₈ in the non-saturatedconductive state. Accordingly, the potential of the higher potentialdigit line DL is raised to Vcc through FET Q₈.

As explained above, the discharge of the lower potential digit linesaffects the memory cells, resulting in malfunction.

Referring to FIGS. 3 and 4, a memory circuit according to one embodimentof the invention is described. In FIGS. 3 and 4, elements correspondingto those in FIGS. 1 and 2 are designated by the same references.

This embodiment is achieved by employing word line noise preventingcircuits NP₁ ' to NP_(n) ' in place of the circuits NP₁ to NP_(n) inFIG. 1. The word line noise preventing circuit NP₁ ' is composed of aseries connection of FETs Q₁₈ and Q₂₀ connected between the word lineWL₁ and the ground potential, FET Q₁₇ connected between the prechargenode N₁ and the ground potential and forming a flip-flop with FET Q₁₇and a precharge FET Q₁₉. A control signal φ_(N) is applied to a gate ofFET Q₂₀. When the signal φ_(N) is high (Vcc) in level, EFT Q₂₀ isconductive thereby to enable the noise preventing circuit NP₁ '. Whileφ_(N) is low (GND) in level, FET Q₂₀ is non-conductive thereby acting todisable the circuit NP₁ '. The other noise preventing circuits NP₂ ' toNP_(n) ' have the same construction as NP₁ '.

The signal φ_(N) is rendered low in level when the sense amplifiersdischarge the lower potential side digit lines so that the noisepreventing circuits NP₁ ' to NP_(n) ' are disabled. Accordingly, thenon-selected word lines are not clamped to the ground potential but laidfloating state. After discharge of the digit lines by the senseamplifiers and during the period when the active pull-up circuits areenabled thereby to raise the higher potential side digit linesapproximately to Vcc, the signal φ_(N) is made high to enable the noisepreventing circuits NP₁ ' to NP_(n) '. Therefore, the non-selected wordlines are clamped to the ground potential without being affected by therise of the higher potential side digit lines by the active pull-upcircuits.

The operation of this embodiment is explained with reference to FIG. 4.

The operation from the time point t1 to the time t4 is the same as thatof the circuit of FIG. 1 except the noise preventing circuits. Namely,during this period from t1 to t4, the signal φN assumes the low level(GND) to render FET Q20 non-conductive in each of the noise preventingcircuits. Therefore, the noise preventing circuits NPi to NPn' aredisabled so that the non-selected word lines are placed in a floatingstate. Subsequently, at a time t4, the signal SE1 has fallen from Vcc tothe ground potential so that the sense amplifiers start theiramplification operations, under the disabled state of the noisepreventing circuits. Accordingly, the lower potential side digit linesare discharged. In response to the discharge of the digit lines, thesubstrate bias voltage VSUB and the potential VA of the memory cellcapacitors Cs storing "0" level are lowered to negative values,respectively. However, in this instance the noise preventing circuitsNPi to NPn' are disabled and therefore, the potential of thenon-selected word lines are also lowered to a negative potential due tocoupling between the substrate and the word lines.

Accordingly, even when the potential VA of the memory cell capacitor Csis lowered to a negative value, the gate potential of the memory celltransistor QM coupled to the non-selected word line is simultaneouslylowered to a negative value, as illustrated. Therefore, the memory celltransistor QM can be kept at non-conducting state. Accordingly,destruction of stored data and/or mutual interference among memory cellscan be effectively avoided.

Subsequently, after the potential of the non-selected word line WLN, thesubstrate bias voltage VSUB and the potential VA of the memory cellcapacitor CS return to their predetermined values at a time t4', thesignal φN is raised to VCC thereby to enable the noise preventingcircuits NPi to NPn'. Accordingly, the non-selected word lines areclamped to the ground potential. Then, at a time t5, the signal SE2 israised to Vcc and the active pull-up circuits are enabled. Thus, thehigher potential side digit lines are raised to Vcc by the pull-upcircuit. The side of the higher potential side digit lines affect thenon-selected word lines so as to raise their potentials. However, inthis instance, the non-selected word lines are clamped to the groundpotential by the noise preventing circuits, such affection can beeffectively avoided.

As to the waveform of φN, it is also possible to maintain it at highduring the period from t1 to t4 as illustrated by the dotted line in theFigure.

FIG. 5 shows another embodiment of the invention. This embodiment isfeatured in that FET Q20 receiving φN and the precharge FET Q19 in FIG.3 are commonly provided as FETs Q20' and Q19' for a plurality of noisepreventing circuits NP1" to NPn". According to this feature, the size ofeach noise preventing circuit can be reduced to enhance high densitystructure of a memory circuit.

I claim:
 1. A memory circuit comprising a pair of digit lines, aplurality of word lines intersecting with said pair of digit lines, aplurality of memory cells coupled to said digit lines and said wordlines, a word line selection circuit for selecting one of said wordlines, a sense amplifier provided for said pair of digit lines, saidsense amplifier operatively discharging one of said pair of digit lines,a pull up circuit provided for said pair of digit lines, said pull upcircuit operatively raising a potential of the other of said digit lineto a power voltage after the discharge of said one of said digit lines,a plurality of word line noise preventing circuits each coupled to eachone of said word lines, each of said noise preventing circuitsoperatively clamping the associated word line in the case where saidassociated word line is not selected, and control means for controllingsaid noise preventing circuits in such manner that said noise preventingcircuits are disenabled when said sense amplifier discharges one of saiddigit lines and enabled when said pull up circuit raises a potential ofthe other of said digit lines.
 2. The memory circuit according to claim1, in which each of said memory cells is composed of a storage capacitorand a transistor having a gate coupled to one of said word lines and asource-drain path coupled between said storage capacitor and one of saiddigit lines.
 3. The memory circuit according to claim 1, in which eachof said noise preventing circuits includes a first transistor having asource-drain path coupled between a first node and a reference voltagesource, a second transistor having a source-drain path coupled betweenone of said word lines and a second node, a gate of said firsttransistor being connected to said one of word lines, a gate of saidsecond transistor being connected to said first node.
 4. The memorycircuit according to claim 3, in which said control means includes aswitch coupled between said second node and said reference voltagesource.
 5. The memory circuit according to claim 1, further comprises aprecharge circuit for operatively precharging said pair of digit linesto a predetermined potential.
 6. A memory circuit comprising a pair ofdigit lines; a plurality of word lines intersecting with said digitlines; a sense amplifier coupled to said pair of digit lines; a wordline selection circuit for selecting one of said word lines; a pluralityof memory cells each coupled to one of said word lines and one of saiddigit lines; a plurality of noise preventing circuits each coupled toeach one of said word lines; each of said noise preventing circuitsincluding a first transistor having a current path coupled between afirst node and a reference voltage terminal and having a gate coupled toa second node, and a second transistor having a current path coupledbetween said second node and a third node and having a gate coupled tosaid first node, said second node being connected to one of said wordlines; a precharge circuit for operatively precharging said first nodein each of said noise preventing circuit, and a switch circuit coupledbetween said reference voltage terminal and said third node in each ofsaid noise preventing circuit.
 7. A memory circuit comprising a pair ofdigit lines, a plurality of word lines intersecting with said pair ofdigit lines, a plurality of memory cells coupled to said digit lines andsaid word lines, a word line selection circuit for selecting one of saidword lines, a sense amplifier provided for said pair of digit lines,said sense amplifier operatively discharging one of said pair of digitlines, a plurality of word line noise preventing circuits each coupledto each one of said word lines, each of said noise preventing circuitsoperatively clamping the associated word line in the case where saidassociated word line is not selected, and control means for controllingsaid noise preventing circuits in such manner that said noise preventingcircuits are disenabled when said sense amplifier discharges one of saiddigit lines.